Regions of a conventional complementary metal-oxide-semiconductor field-effect transistor (CMOS) device may serve as or form a plurality of bipolar junction transistors (BJTs) (e.g., coupled in a loop). For example, a conventional CMOS device may include a PFET adjacent a first side of a shallow trench isolation (STI) oxide region and an NFET adjacent a second side of the STI oxide region. Diffusion regions and/or wells of the NFET and PFET may form a first BJT coupled to a second BJT in a loop.
A particle that strikes the CMOS device, a voltage induced in the CMOS device and/or a similar occurrence may initiate a regenerative action and induce a current in the BJT loop. Due to a gain of the BJT loop, the current through the BJT loop may continue to increase until the device is destroyed (a condition referred to as “latchup”). Accordingly, improved CMOS devices that prevent latchup and methods of manufacturing the same are desired.